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\title{1996 CS 181a Class Outline}

\subsection*{Instructor}

\noindent Mika Nystr\"{o}m

\noindent Jorgensen 66

\noindent Phone: x6237

\noindent Mailcode: 256-80

\noindent mika@cs.caltech.edu (send class email to cs181@cs.caltech.edu)

\subsection*{Teaching Assistants}

\noindent Mark Neidengard

\noindent mneideng@ugcs.caltech.edu (send class email to cs181@cs.caltech.edu)

\subsection*{Lectures}

\noindent The class meets on Tuesdays and Thursdays 1:30-3:00 in Jorgensen 74.

\subsection*{Syllabus}

\noindent{\large CS/EE 181 abc. VLSI Design Laboratory}
{\it 12 units (3-6-3); first,second,third terms.}
{\it Prerequisites: CS/EE 4 and CS 10, or equivalent.}
Digital integrated system design, with projects involving the design, verification, and testing of high-complexity CSMOS circuits. First-term lecture and homework topics emphasize disciplined design, and include CMOS logic, layout, and timing; computer-aided design and analysis tools; and electrical and performance considerations.
Each student is required in the first term to complete individually the design, layout, and verification of a moderately complex integrated circuit.
Advanced topics second and third terms include self-timed design, computer architecture, and other topics that vary year by year.
Projects are large-scale designs done by teams.

\subsection*{Textbook}

No textbook is required for the course. The following two books are
recommended reading.

\bigskip

Mead and Conway, Introduction to VLSI Systems, Addison-Wesley.

\bigskip

Weste and Eshragian, Principles of CMOS VLSI Design (2nd ed.), Addison-Wesley.

\subsection*{Grading}


\subsection*{Cooperation}

(URL: http://www.cs.caltech.edu:/$\tilde{~}$cs181/)
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